The invention is related generally to electronic circuits, and more particularly to a circuit and method for recovering synchronization information from a signal. In one embodiment, the circuit signals the beginning of a data stream to a Viterbi detector, and the circuit is separate from the Viterbi detector. In another embodiment, the circuit has a greater noise immunity than prior synchronization circuits, and thus can more accurately recover synchronization information from a read signal having a reduced signal-to-noise ratio (SNR). In yet another embodiment, the circuit can recover the synchronization information in fewer cycles, and thus with fewer pad bits, than prior synchronization circuits.
FIG. 1 is a partial block diagram of a conventional disk drive 10, which includes a magnetic storage disk 12 and a read channel 14 for reading data-synchronization information and encoded data from the disk 12. The read channel 14 includes a read head 16 for sensing the data-synchronization information and the encoded data stored on the disk 12 and for generating a corresponding read signal. A clock circuit 18 recovers a clock from the read signal, and a read circuit 20 amplifies the read signal, samples the read signal on the edges of the clock, and digitizes the samples. Using the data-synchronization information to locate the first data bit, the Viterbi detector 22 recovers the encoded data from the digitized samples. A decoder 24, which uses the data-synchronization information to locate the first recovered data bit from the Viterbi detector 22, decodes the recovered data.
FIG. 2 is a timing diagram of the data-synchronization information and the data stored on the disk 12 (FIG. 1) in the order sensed by the read head 16 (FIG. 1). The disk 12 includes a number of concentric tracks (not shown) that each include one or more respective data sectors, each sector including respective data-storage locations. Each data sector to which data has been written stores a data forerunner and the data in its storage locations. The data forerunner includes a synchronization wedge, a preamble, a synchronization mark (hereinafter sync mark), and a pad. Typically, the disk drive 10 (FIG. 1) writes a respective wedge at the beginning of each data sector during the formatting of the disk 12, and writes the preamble, sync mark, and pad to a data sector each time one writes data to the data sector. As the disk 12 rotates, the read head 16 first senses the wedge at time t0, and then senses the preamble, sync mark, pad, and data at relative times t1, t2, t3, and t4, respectively.
Referring to FIGS. 1 and 2, the read channel 14 operates as follows. A front-end circuit (not shown) receives the read signal and activates the clock circuit 18 in response to the synchronization wedge. Once activated, the clock circuit 18, which typically includes a phase-locked loop (PLL, not shown), aligns the phase and frequency of the clock signal with the phase and frequency of the preamble. Next, the Viterbi detector 22 recovers from the sync mark the timexe2x80x94typically the clock edgexe2x80x94at which the detector 22 will receive the first data sample. The pad includes a number of don""t-care bits, and thus provides a delay between the end of the sync mark and the beginning of the data. This delay allows the detector 22 to reliably recover this first-data-sample time before it actually occurs. The detector 22 then begins recovering the data from the read signal at the first-data-sample time. After a delay equal to its latency, the detector 22 provides the first recovered data bit to the decoder 24 at a first-recovered-bit time, and synchronizes the decoder 24 such that it begins decoding the recovered data at the first-recovered-bit time. But as discussed below, if the detector 22 fails to accurately recover the first-data-sample time, then it begins recovering the data at the wrong sample time, and thus typically generates fatal read errors.
One problem with the Viterbi detector 22 is that it often requires the read signal to have a relatively high signal-to-noise ratio (SNR), and thus often limits the data-storage density, and thus the data-storage capacity, of the disk 12.
The storage density of the disk 12 is a function of the distances between the storage locations within the data sectors and the distances between the disk tracks. The smaller these distances, the greater the storage density, and vice-versa. The storage capacity of the disk 12 is proportional to its surface area and its storage density. But because the diameter of the disk 12, and thus its surface area, is typically constrained to industry-standard sizes, the option of increasing the surface area of the disk 12 to increase its storage capacity is usually unavailable to disk-drive manufacturers. Therefore, increasing the storage density is typically the only available technique for increasing the storage capacity of the disk 12.
Typically, the greater the storage density of the disk 12, the closer the surrounding storage locations are to the read head 16 while it is reading the surrounded storage location, and thus the lower the signal-to-noise ratio (SNR) of the read signal. Specifically, the closer the surrounding locations are to the read head 16, the greater the magnitudes of the magnetic fields that these locations respectively generate at the head 16, and thus the greater the Inter Symbol Interference (ISI). The greater the ISI, the smaller the root-mean-square (RMS) amplitude of the read signal. In addition, as the storage density of the disk 12 increases, the media noise also increases. Generally, the media noise results from the uncertainty in the shapes of the read pulses that compose the read signal. This uncertainty is caused by unpredictable variations in the relative positions of the storage locations from one data-write cycle to the next. Moreover, for a given spin rate of the disk 12, as one increases the linear storage density within the data sectors, he/she must also increase the bandwidth of the read head 16 to accommodate the increased number of storage locations that the read head 16 must sense in a given time period. This increase in bandwidth causes a proportional increase in the white noise generated by the read head 16. The SNR of the read signal for a particular storage location is the ratio of the RMS amplitude of the corresponding portion of the read signal to the sum of the amplitudes of the corresponding media and white noise. Thus, the lower the RMS amplitude of the read signal and the greater the amplitudes of the media and/or white noise, the lower the SNR of the read signal.
Unfortunately, as the SNR of the read signal decreases, the data-recovery speed of the Viterbi detector 20 often decreases as well. Specifically, the lower the SNR of the read signal, the lower the accuracy of the detector 20. As discussed above, the failure of the detector 20 to accurately recover the first-data-sample time from the sync mark often causes serious read errors. If the error processing circuit (not shown) initially detects a read error, then it tries to correct the error using conventional error-correction techniques. If the processing circuit cannot correct the error using these techniquesxe2x80x94typically the case when the detector 20 recovers an inaccurate first-data-sample timexe2x80x94then it identifies the error as xe2x80x9cfatalxe2x80x9d and instructs the read channel 14 to re-read the data from the disk 12. The time needed by the processing circuit for error detection and error correction and the time needed by the read channel 14 for data re-read increase as the number and severity of the read errors increase. As the error-processing and data re-read times increase, the effective data-read speed of the channel 14, and thus of the disk drive 10, decreases.
Therefore, to maintain an acceptable effective data-read speed, the manufacture rates the Viterbi detector 22 for a minimum read-signal SNR. Unfortunately, if the SNR of the read signal falls below this minimum, then the accuracy of the read channel 14 often degrades such that at best, the effective data-read speed of the disk drive 10 falls below its maximum rated speed, and at worst, the disk drive 10 cannot accurately read the stored data.
Referring again to FIGS. 1 and 2, another problem is that the Viterbi detector 22 recovers both the data-synchronization information and the data. Unfortunately, this dual functionality often increases the circuit complexity and limits the effective data-recovery speed of the detector 22.
Furthermore, including the pad in the data forerunner reduces the amount of data that the respective data sector can hold. But eliminating or reducing the length of the pad may decrease the sync-recovery accuracy of the Viterbi detector 22, and thus may increase the probability of a fatal read error that requires the read channel 14 to reread the data.
Detailed descriptions of the structure and operation of a conventional Viterbi detector such as the Viterbi detector 22 are available in many references and in the background section of heretofore incorporated U.S. patent application Ser. No. 09/409,923.
In one aspect of the invention, a synchronizer circuit includes an input terminal, an output terminal, and a recovery circuit coupled to the input and output terminals. The input terminal receives an input signal that includes a sync mark, and the recovery circuit is operable to recover the sync mark from the input signal and to generate a synchronization signal on the output terminal in response to the recovered synchronization mark.
For example, such a synchronizer circuit can recover the synchronization mark from a read signal and locate the beginning of a data stream for a Viterbi detector that is separate from the circuit. By performing the sync-recovery function in a separate circuit, one can reduce the complexity and increase the data-recovery speed of the Viterbi detector.
In another aspect of the invention, the synchronizer circuit recovers the sync mark by executing state-transition routines in alignment with the input signal.
For example, one can align the synchronizer circuit""s state-transition routines to the preamble of the read signal. Such alignment increases the circuit""s noise immunity, and thus allows the circuit to recover the sync mark from a read signal having a SNR that is lower than the minimum read-signal SNR of prior sync-recovery circuits. Furthermore, such alignment reduces the time needed for the circuit to reliably detect the sync mark, and thus allows one to shorten the pad of the data forerunner.